Among the efforts to increase device density in integrated circuits, three-dimensional integrated circuits (3DICs) are commonly used. Through-substrate vias (TSV) are often used in 3DIC for connecting multiple dies to package substrates. There are several commonly used approaches for forming TSVs. For example, TSVs may be formed before inter-layer dielectric (ILD) is formed (which approach is referred to as a via-first approach), or formed after the formation of ILD and before the formation of the bottom metal layer (M1, which approach is referred to as a via-middle approach). TSVs may also be formed after all metal layers and passivation layers are formed, and may be formed from the front side or the back side of the respective wafers/chips, which approaches are referred to as via-last approaches.
In the manufacturing of TSVs using the via-last approach, wherein the TSVs are formed from the backside of a wafer, an etch needs to be performed to etch through a semiconductor substrate, shallow-trench isolation (STI) pads, and an inter-layer dielectric over the STI pads, so that the metal pads in a bottom metal layer are exposed through the respective TSV openings. However, serious lateral etching may occur in the ILD, causing the portions of the TSV openings in the ILD to be wider than the portions of the TSV openings in the semiconductor substrate. This results in difficulty in the formation of isolation layers, which are formed on the sidewall of the TSV openings. Further, during the formation of the TSV openings, the metal pads in the bottom metal layer may be undesirably etched. Since the metal pads are very thin, they may also be etched through.